Enabling multiple arrays to expose a single coherent image of one or more logical units may be done with in-band caching devices. For example, a caching device may be placed in front of each array and may manage the coherency between each caching device and their corresponding array. Unfortunately, the problem with this arrangement is that servers accessing the data may no longer see the personality of the array but may only see the personality of a new caching device. This, in turn, may adversely impact the general and fault management software of the system.
Alternatively, the caching logic of the in-band caching device may be embedded within the array itself and, in particular, within the array software stack. Unfortunately, the problem with this approach is the increased complexity of the software stack within the array. Specifically, increased code path lengths may lead to lower performance and more error-prone designs.